The Design of on Oversampling ADC with Low Clock Feedthrough Noise and OP-Amp Gain-Compensation
碩士 === 淡江大學 === 電機工程學系 === 84 === The new design of a switched-capacitor(SC) delta-sigma modulator(DSM) is proposed. Generally speaking, the performance of a DSM is degraded due to theop-amp gain and clock feedthrough noise, and the ri...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1996
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| Online Access: | http://ndltd.ncl.edu.tw/handle/83813807608719011816 |