Reducing Area Cost with low miss rate for On-chip Caches
碩士 === 國立中正大學 === 資訊工程學系 === 85 === Several new cache architecture approaches have been proposed todiminish the tag area, miss rate, or reduce access time, for example, CAT(catching address tags), decoupled sectored cache, PAD(parti...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/31088363570696468399 |