VLSI Implementation of High-Speed Double-Error Correcting Binary BCH decoder
碩士 === 中華大學 === 電機工程研究所 === 85 === A real-time high-speed double-error-correcting binary BC decoder is implemented in the thesis. The modified step-by-step method was adopted in the design for avoiding the task of finding error location polynomial and inverse operations. The presented decoder...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/33887706824069311537 |