IDDQ Testing:A Backtracking Method to Generate Complete Test Patterns for Leakage Faults

• Main Authors: Wu, Jyh-wei, 吳志偉
• Other Authors: S.J. Wang
• Format: Others
• Language: zh-TW
• Published: 1997
• Online Access: http://ndltd.ncl.edu.tw/handle/01215259389411270871

碩士 === 國立中興大學 === 資訊科學研究所 === 85 === Within a static CMOS circuit, a lot of faults are bridging faults and leakage faults. Many researches forcus on the two fault models. And there are many methods to generate IDDQ test patterns to detect bridging faults and leakage faults recently. This paper decribes a backtracking method to generate Supplemental IDDQ test patterns for IDDQ leakage faults. Furthermore, it will be proved that any complete test pattern set generated for stuck-at faults detects all leakage faults (gate-drain short, gate-source short, gate-bulk short, source- bulk short, source-drain short, and bulk-drain short) within a single fully CMOS (SFCMOS). We develop a program named Gen_Test for this purpose. Gen-Test can achieve the gial described above if the circuit contains only inverters, NAND2, NAND3, OR2, and NOR3 gates and all stuck-at faults are detectable.The number of test patterns generated by Gen_test may be very small, even a constant. For instant, in a fanout-free circuit containing only NAND3 gates, weneed 4 test patterns to detect all leakage faults. As the number of fanout within a circuit increases, the number of test patterns for leakagefaults increases, too.The advantages of Gen_Test includes: (1) the number of test patterns is small, (2) the test patterns can detect all leakage faults, in which some this patterns are for bridging faults and multiple stuck-at faults, (3) it improves reliability.the disadvantages of Gen_Test are: (1) it wastes memory during test pattern generation for leakage faults.(2) It is time consuming if the number of fanout within a circuit is too large.