Simulation and Performance Evaluation of NSC98 Microprocessor: Register Renaming and Out-of-order Execution
碩士 === 國立交通大學 === 資訊工程學系 === 85 === The objective of this thesis is to build a simulator to simulate and evaluate a x86 compatible supercalar microprocessor, namely NSC98. Theperformance evaluation will focus on the implementation o...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1997
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/39613668371644832007 |