High Performance Hydrogenated Amorphous Silicon Thin Film Devices Fabricated by Plasma Enhanced Chemical Vapor Deposition Method

• Main Authors: Lin, Chiung-Wei, 林炯暐
• Other Authors: Chang Chun-Yen
• Format: Others
• Language: zh-TW
• Published: 1997
• Online Access: http://ndltd.ncl.edu.tw/handle/14675563129810011709

博士 === 國立交通大學 === 電子工程學系 === 85 === aaaaa本論文中, 我們利用自行設計組裝之電漿輔助化學氣相沉積系統( PECVD)成長不同組成特性的氮化矽膜應用於非晶矽電晶體製作來比較其電 氣特性的差異.當氨氣/矽甲烷流量比提高其所得之氮化矽膜傾向"多氮性" 氮化矽膜(nitrogen-rich silicon nitride film), 此種薄膜具有較輕微 的載子補捉現象. 然而相對地, 與後續成長的非晶矽薄膜形成較差的界面 特性, 許多缺陷狀態存於非晶矽薄膜並且影響薄膜電晶體特性. 經過氮氣 退火處理後不僅金屬 -n型非晶矽接觸改善同時氮原子亦會擴散至氮化矽/ 非晶矽界面加上本體非晶矽內部較脆弱矽-氫鍵打斷而氫離子也有部分移 動到此界面來共同改善薄膜電晶體特性.接著, 使用兩個相同結構雙極性 薄膜電晶體整合成共閘極互補式反相器, 其輸出電壓在短短1.31伏特之輸 入電壓範圍完成切換動作. 經過氮氣退火處理後, 實際負載元件與驅動元 件的改善程度差異與所使用退火溫度對於良好反相器之獲得是需要同時考 慮的關鍵. 我們另外提出一種全新結構元件,它以氫稀釋法成長高傳導非 晶矽(HC a-Si:H)提升驅動電流而傳統高阻抗非晶矽(HR a-Si:H)有效地抑 止元件於關閉狀態之載子傳導.此全新結構元件其開/關電流比高達七個數 量級及0.61伏特的臨限電壓,並可以達成4.31cm^2/V.sec的高場效遷移率. 最後提出氫原子補償機制於負偏壓應變時加入對薄膜電晶體穩定性的分 析, 當HR a-Si:H 中矽-氫鍵被打斷,氫離子受吸引到HC a-Si:H填補懸浮 鍵與因偏壓引起之缺陷狀態而改善薄膜電晶體特性. sssssThe effect of various silicon nitride films which is deposited by a home-made PECVD system as gate insulators on the electrical properties of the amor-phous silicon thin film transistor ( TFTs ) have been investigated. As the NH3/SiH4flow flux ratio for SiNx deposition increases, it tends to be N-rich SiNxfilm which possesses few charge be trapped forming a poor contact with subseq-uently deposited a-Si:H layer. Many defect states form in a-Si:H degrading theTFT''s performance with NH3 / SiH4 flow flux ratio. By introducing N-atom ther-mally, they not only suppress the hole-injection due to imrpoved metal/semico- nductor contact but also diffuse into the a-Si:H /SiNx interface to reduce thedensity of surface states. In addition, the weak Si-H bonds in bulk a-Si:H areeasy to be broken and the ionic H- atoms also diffuse into the interface impro-ving the TFT''s performance. Besides, a common gate complementary inverter cir- circuit made by ambipolar a-Si:H TFTs has been completed. The O/ P level can bechanged within I/P range of 1.31 V. Both the balance between annealed load anddriver transistors and annealing temperature is needed for a superior inverter characteristics. Meanwhile,a novel thin film transistor with a vertical offset structure was proposed. A thin HC a-Si:H used to improve drivability while thevertical HR a-Si:H offset film suppresses the OFF-state current.Both annealingand etching effects must be optimized playing a key role improving the qualityof HC a-Si:H that affects TFT''s performance. The ON/OFF current ratio achieves8.07E+6 and the threshold voltage is only 0.61 V.The field effect mobility can approach 4.31 cm^2/V.s.At last, a new mechanism that affects TFT''s reliability is proposed. The H-atom compensation resulting from the break of weak bonds in the HR a-Si:H offset layer would reduce the bias stress induced states locatedon the gate insulator/channel interface with negative bias stress that improvethe switching operation and drivability for TFTs. The trade-off for H-atom co- mpensation and bias stress induced state creation should be taken into accountfor realizing the detailed instability mechanism of HC a-Si:H TFTs.