| Summary: | 碩士 === 國立交通大學 === 電子工程學系 === 85 === In this thesis, a VLSI architecture for motion estimation baed
on a hierarchical-search block matching algorithm (HSBMA) is
developed. The proposed architecture can deal with the full-
search block matching algorithm(FSBMA) as well. To meet the
real-time requirement of MPEG-2 MP@ML, parallelprocessing is in
great demand. Adopting semi-systolic array (SSA) architecture,
100% hardware efficiency can be achieved within
processingelement (PE) array. This proposed architecture mainly
consists of fiveunits, namely control unit, memory bank unit,
2-D processing element array,summation unit and comparison unit.
The key feature of this design is that the maximum possible
reuse of overlapped search area pixels is considered,which can
reduce the bandwidth of the frame memory interface. Also,
scalabledesign is included. By cascading several chips, we can
process the referenceblock with different sizes. Based on 0.6um
Compass library and TSMC 0.6um SPDM process technology, clock up
to 71.4 MHz can be achieved. The resultimplies that this chip
can meet the real time requirement of MPEG-2 MP@MLencoding.
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