| Summary: | 博士 === 國立交通大學 === 電子工程學系 === 85 === This dissertation studies the strategies for improving the
testing efficiency and the testability for synchronous
sequential circuits. In sequential circuits, some faults are
hard or impossible to begenerated tests, which degrades the
efficiency of a test generator very much. For the untestable
faults, it is worthwhile to identify them beforehand in order
not to vainly search test patterns. A simpleyet efficient
method is proposed to identify four types of untestablefaults in
sequential circuits. The method makes use of the unknown
initial state of flip-flops and propagates the characteristics
throughout the circuit to find the uncontrollable lines and
flip-flops. The untestable faults are classified into four
types and are identified from the simulated results by rules.
Comparing the results to other methods, it is obvious that our
method can identify more untestable faults in short time. In
addition to untestable faults, test generators including
justification process have another problem that they may justify
the flip-flops into invalid states. These states cannot be
reached from the initial state of the circuit under whatever the
input sequences. If not knowing or learning these invalid
states information before or during test generation, the test
generator may cost a lot of time for justification and the
process may go into an infinite loop or abort at last. To
prevent entering such a predicament, three algorithms are
proposed to search the invalid states of a sequential circuit.
The first algorithm explores all the valid states from an
unknown initial state to search the complete set of invalid
states. The second algorithm finds the complete set of invalid
states by searching the reachable states for each state. The
third algorithm searches the invalid states that need to be
known for test generation to help stop justification early by
analyzing dependency among flip-flops to simulate each partial
circuit. Experimental results show that the algorithms can
identify invalid states in short time. The obtained invalid
states were also used in test generation to show that they can
improve test generation significantly in the test generation
time, the fault coverage and the detection efficiency,
especially for larger circuits and those that were difficult to
be generated tests. The information about invalid states can
also be used to aid testable design. A method is proposed to
select flip-flops for partial reset and/or partial scan for
sequential circuits to increase their testability. From an
initial test generation, information on required states for
activating faults and the number of faults which can be
propagated to flip-flops are obtained. These are analyzed and
quantified, in which the required states covered by invalid
states are also considered, to obtain the selection weights of
flip-flops for reset or scan. Experiments show that this method
can select less number of flip-flops for partial reset and scan
while produce more testable circuits for benchmark circuits.
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