| Summary: | 碩士 === 國立交通大學 === 電子工程學系 === 85 === TDDB and latch-up in deep submicron CMOS are studied in
this thesis. TDDB is discussed in the Part A with emphasis on
developing a simulator for instrinsic and B-mode oxide failures.
The Part B investigates CMOS latch-up and concentrates on the
modeling of the holding point. In the Part A, a C-language
program is developed to simulate the TDDB distribution of ultra-
thin oxides based on the work by R. Degraeve et al. in 1995.
Basic concepts of Monte-Carlo method and some parameters for the
simulation are discussed in more detail. Combining the program
with the concept of oxide thinning by J. C. Lee et al., a new
idea is proposed to simulate the statistical distribution of B-
mode oxide failures. The modeling of the holding point in
the Part B is based on a physically-based analytical model
considering conductivity modulation and base push-outby J. A.
Seitchik et al. in 1987. The internal behavior of parasitic SCR
in CMOS circuits is studied completely by a two-dimensional
device simulator. With the help of the above two results, a
compact model for the holding voltage is constructed. Then
incorporating a structure-oriented holding current formula into
this model, a compact, closed-form expression for the holding
voltage is produced. Finally, a full model for the holding point
is developed. It is surprising that the full model can explain
the temperature behavior of latch-up very well. Both of the
compact and full models are thoroughly judged by experimental
results.
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