Latency Analysis of Hierarchical Self-Clocked Queueing Algorithm
碩士 === 國立交通大學 === 電信研究所 === 85 === A hardware-efficient implementation for theself-clocked fair queueing (SCFQ)traffic scheduling algorithm usingsorting bins has recently been proposed. This architecture is suitable for a moderate range o...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/74746503154296707297 |