The Implementation and Analysis of All Digital Phase-Locked Loop
碩士 === 國立中央大學 === 電機工程學系 === 85 === In this thesis, an all digital phase-locked loop(ADPLL) is proposed. The architecture of the proposed ADPLL is based on the ADPLL proposed by Motorola in 1995, but some modifications are made. A digitally...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/65915664750386172130 |