A 3V, Fast lock-in Phase-locked Loop for High Speed System
碩士 === 國立清華大學 === 電機工程學系 === 85 === In this thesis, we propose a 3V, fast lock-in phase-locked loop with wide frequency range for high speed data systems. This PLL, which is used as a frequency synthesizer for clock/data recovery, is realized by a charge-...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/03909307916994524511 |