The Design and Realization of Clock Deskew Buffer Circuit for High Speed Digital Signal
碩士 === 國立臺灣大學 === 電機工程學系 === 85 === Due to constant development and progress in integrated circuit process,digital system is becoming more and more complicated,and the operating clock frequency is constantly increasing.Nowadays,a digit...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/53346578981860721307 |