| Summary: | 碩士 === 國立臺灣大學 === 電機工程學系 === 85 === Due to constant development and progress in integrated
circuit process,digital system is becoming more and more
complicated,and the operating clock frequency is constantly
increasing.Nowadays,a digital system may contain several chips
of different purposes.And these chips operate synchronously
according to the system clock produced by a clock generator.
Clock skew due to clock distribution on printed circuit board
has thus become an important factor which may affect the proper
work between chips in the synchronous system. In this
thesis,several architectures which may be used to correct clock
skew will be introduced.And a clock deskew chip had been
designed based on the concept of delay locked loop.We used two
identical-length transmissionpaths (one of them is a feedback
path) to transmit the clock signal and detect clock skew.From
the test and simulation result,we have demonotrated that
thisclock deskew system can operate between 10MHz and 80MHz,and
allow the propagation delay of transmission paths to be 0.5~0.8
ns(i.e. 3.3ns clock skew).In this clock skew range,clock skew
can be corrected to 300ps.And in the operating frequency range,
clock jitter is within 170ps (peak-to-peak).
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