A CMOS Multiplier Circuit using a 1.5V CMOS Logic Circuit
碩士 === 國立臺灣大學 === 電機工程學系 === 85 === This thesis reports a 1.5V high-speed 8X8 multiplier circuit usingthe Wallace tree reduction architecture and true-single- phase bootstrappeddyanmic and static circuit techniques. Based on a 0.8um CMO...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/66188657075161112912 |