A PLDCO-based FLL for All Digital Clock Recovery Circuit
碩士 === 國立臺灣大學 === 電機工程學系 === 85 === This thesis is based on a new frequency locked loop(FLL) circuit for all digital clock recovery circuit called the PLDCO- based FLL circuit . The piecewise linear digital controlled oscillator(PLDCO) wh...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/06065086292931122381 |