A PLDCO-based FLL for All Digital Clock Recovery Circuit
碩士 === 國立臺灣大學 === 電機工程學系 === 85 === This thesis is based on a new frequency locked loop(FLL) circuit for all digital clock recovery circuit called the PLDCO- based FLL circuit . The piecewise linear digital controlled oscillator(PLDCO) wh...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1997
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| Online Access: | http://ndltd.ncl.edu.tw/handle/06065086292931122381 |
| Summary: | 碩士 === 國立臺灣大學 === 電機工程學系 === 85 === This thesis is based on a new frequency locked loop(FLL)
circuit for all digital clock recovery circuit called the PLDCO-
based FLL circuit . The piecewise linear digital controlled
oscillator(PLDCO) which is a modified version of the digital
control oscillator(DCO) is the heart of this proposed circuit.
The PLDCO has features of small mode transistion jitter,simple
control algorithm and has the same jitter of each nearby contrl
wordtransition. A propotype of this FLL circuit chip for all
digital clock recovery circuitis implemented with 0.6um CMOS
process. The simulation result shows that thischip operate under
the range from 60.95MHz to 210.75Mhz across all the processes
and normal temperatures, running at 16X the reference clock
frequency.This chip has 4142 transistors and the core size is
2078.3um * 1497.3um
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