Verification for Asynchronous Circuits
碩士 === 國立臺灣大學 === 電機工程學研究所 === 85 === This dissertation presents a verifying methodology on signal transition graph (STG) for asynchronous circuits which are required to be hazard-free under unbounded gate delay model. All the theoretical bases are based on a newly proposed model; that is, Ext...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Online Access: | http://ndltd.ncl.edu.tw/handle/45616646307910746737 |