| Summary: | 碩士 === 中原大學 === 資訊工程研究所 === 86 === In this thesis, we propose a new technology mapping, called ArchMap,for LUT-based FPGAs with the hard-wired connection architecture in PLBs. To minimize the delay in the mapped network.ArchMap are divided into two step as follows:1. Mapping the initial circuit to a LUT network: Instead of mapping the initial circuit to a K-LUT network for a fixed K, we try to map the initial circuit to a LUT network more suitable to the desired architecture using the multiple K-feasible cut technique.2. Mapping the LUT network to a PLB network: An architecture-specific labeling procedure is designed to map the LUT network to a PLB network. In our experiments, we use MCNC benchmark circuit as test circuits andchoose Xilinx XC4000 series FPGAs as the target architecture. Experimentalresults show that ArchMap reduce the depth of CLB network by 39.74% and reduce the number of CLBs by 27.61% compared with that obtained by MIS-pga-delay plus match_4k. On the other hand, ArchMap obtained 7.69% of improvement of the depth of CLB network and only 1.86% of drawback of the number of CLBs compared with FlowMap script of RASP.
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