The Analysis and Design of a 10-Bit Three Stages Pipelined Analog-to-Digital Converter

• Main Authors: Lin, Su-Chia, 林樹嘉
• Other Authors: Liou Wan-Rone
• Format: Others
• Language: zh-TW
• Published: 1998
• Online Access: http://ndltd.ncl.edu.tw/handle/47755008262309895361

碩士 === 國立海洋大學 === 電機工程學系 === 86 === In this thesis, we design a 10-bit, 20MSamples/s, three stagespipelined CMOS analog-to-digital converter (ADC). The framework contains three 4-bit stages. The main subcircuits of the ADC are sample/hold circuit, 4-bit flash A/D converter, 4-bit D/A converter, subtractor, gain circuit, clock generator, encoder, register, and adder.The sample/hold circuit is implemented with switched-capacitor techniques. Switched- capacitor requires only relative accurate capacitance. It is therefore much easier to be fabricated for today''s processing technology. The simulation results show that the comparator has 25 MHz samplingrate and 10mV accuracy, the operational amplifier has 85 dB DC gain,and the overall circuit of ADC has 20 MHz sampling rate and ±0.5LSB integral nonlinearity. The comparator and the operational amplifier have been fabricated. The measured results show that the sampling rate ofcomparator can reach 5 MHz, and the operational amplifier has 63 dB DCgain. The input range of ADC is from 1.25V to 3.75V. Power supply of5V is used the design of ADC chip. The coverter is fabricated with UMC 0.5μm double-poly-double-metal n-well CMOS technology. The powerdissipation of the ADC is about 200mW. While the layout of the core circuit is 2.70mm×0.95mm.