Clock Synchronizer for High Speed Digital Systems
碩士 === 國立臺灣大學 === 電機工程學系 === 86 === In this thesis, two architectures of the clock synchronizer that delivers synchronous clock to multiple targets in high-speed digital systems are realized. Based on the consept of delay locked loo...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1998
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/71191213067590937880 |