A Chip Design and Implementation of 13-bit High-Order Oversampling Analog-to-Digital Converter
碩士 === 元智大學 === 電資與資訊工程研究所 === 86 === In this thesis, we propose a 13-bit, 4-order with single bit output oversampling modulator chip. The signal bandwidth is 80KHz and the specification is fit for the ISDN U interface. Different from the conventional ADC...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Online Access: | http://ndltd.ncl.edu.tw/handle/75926171303730476878 |