Reducing Test Application Time by Scan Flip-Flop Sharing
碩士 === 國立中正大學 === 資訊工程研究所 === 87 === In this research, we attempt to reduce the test application time while preserving the test quality or the fault coverage for circuit testing. The goal is achieved by reducing the number of scan flip-flops required for a scan-based design, and the basic...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/75873306236375071400 |