TU-2 Mapper Design
碩士 === 國立中正大學 === 電機工程研究所 === 87 === In Synchronous Digital Hierarchy (SDH) Network, Tributary Unit 2 (TU-2) maps the DS2 signal into a TU-2 superframe with payload pointer and path overhead. In this thesis, TU-2 mapper is designed by Xilinx FPGAs for transmit and receive device. A protot...
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| Format: | Others |
| Language: | en_US |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/84302501790883229769 |
| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 87 === In Synchronous Digital Hierarchy (SDH) Network, Tributary Unit 2 (TU-2) maps the DS2 signal into a TU-2 superframe with payload pointer and path overhead. In this thesis, TU-2 mapper is designed by Xilinx FPGAs for transmit and receive device. A prototype circuit board is built with the designed TU-2 transmit and receive devices and the loopback test is verified by a transmission test set.
The concatenated VC-2-nc supports broadband signals. Framd based or cell based services can be adapted to VC-2-nc format and transported in the SDH network. The VC-2-nc mapper is verified by Xilinx simulation tool in this thesis.
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