TU-2 Mapper Design

碩士 === 國立中正大學 === 電機工程研究所 === 87 === In Synchronous Digital Hierarchy (SDH) Network, Tributary Unit 2 (TU-2) maps the DS2 signal into a TU-2 superframe with payload pointer and path overhead. In this thesis, TU-2 mapper is designed by Xilinx FPGAs for transmit and receive device. A protot...

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Bibliographic Details
Main Authors: Wen-Jay Chen, 陳文傑
Other Authors: Kou-Tan Wu
Format: Others
Language:en_US
Published: 1999
Online Access:http://ndltd.ncl.edu.tw/handle/84302501790883229769
id ndltd-TW-087CCU00442042
record_format oai_dc
spelling ndltd-TW-087CCU004420422016-02-03T04:32:14Z http://ndltd.ncl.edu.tw/handle/84302501790883229769 TU-2 Mapper Design TU-2映射器設計 Wen-Jay Chen 陳文傑 碩士 國立中正大學 電機工程研究所 87 In Synchronous Digital Hierarchy (SDH) Network, Tributary Unit 2 (TU-2) maps the DS2 signal into a TU-2 superframe with payload pointer and path overhead. In this thesis, TU-2 mapper is designed by Xilinx FPGAs for transmit and receive device. A prototype circuit board is built with the designed TU-2 transmit and receive devices and the loopback test is verified by a transmission test set. The concatenated VC-2-nc supports broadband signals. Framd based or cell based services can be adapted to VC-2-nc format and transported in the SDH network. The VC-2-nc mapper is verified by Xilinx simulation tool in this thesis. Kou-Tan Wu 吳國棟 1999 學位論文 ; thesis 38 en_US
collection NDLTD
language en_US
format Others
sources NDLTD
description 碩士 === 國立中正大學 === 電機工程研究所 === 87 === In Synchronous Digital Hierarchy (SDH) Network, Tributary Unit 2 (TU-2) maps the DS2 signal into a TU-2 superframe with payload pointer and path overhead. In this thesis, TU-2 mapper is designed by Xilinx FPGAs for transmit and receive device. A prototype circuit board is built with the designed TU-2 transmit and receive devices and the loopback test is verified by a transmission test set. The concatenated VC-2-nc supports broadband signals. Framd based or cell based services can be adapted to VC-2-nc format and transported in the SDH network. The VC-2-nc mapper is verified by Xilinx simulation tool in this thesis.
author2 Kou-Tan Wu
author_facet Kou-Tan Wu
Wen-Jay Chen
陳文傑
author Wen-Jay Chen
陳文傑
spellingShingle Wen-Jay Chen
陳文傑
TU-2 Mapper Design
author_sort Wen-Jay Chen
title TU-2 Mapper Design
title_short TU-2 Mapper Design
title_full TU-2 Mapper Design
title_fullStr TU-2 Mapper Design
title_full_unstemmed TU-2 Mapper Design
title_sort tu-2 mapper design
publishDate 1999
url http://ndltd.ncl.edu.tw/handle/84302501790883229769
work_keys_str_mv AT wenjaychen tu2mapperdesign
AT chénwénjié tu2mapperdesign
AT wenjaychen tu2yìngshèqìshèjì
AT chénwénjié tu2yìngshèqìshèjì
_version_ 1718177367482957824