Randomization on Testing in Digital Sequential Logic Circuits

碩士 === 中華大學 === 電機工程學系碩士班 === 87 === Randomization on testing in sequential logic circuits is more complicated and difficult than that on combinational logic circuits. In this thesis, it aims to adopt the method of Markov chain to analyze the random testability for detecting a fault in ci...

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Bibliographic Details
Main Authors:	Ti-Wen Chen, 陳文
Other Authors:	Jwu-E Chen
Format:	Others
Language:	zh-TW
Published:	1999
Online Access:	http://ndltd.ncl.edu.tw/handle/54400850713916137407

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spelling	ndltd-TW-087CHPI04420262016-02-03T04:32:22Z http://ndltd.ncl.edu.tw/handle/54400850713916137407 Randomization on Testing in Digital Sequential Logic Circuits 數位循序邏輯電路測試的隨機性 Ti-Wen Chen 陳文碩士中華大學電機工程學系碩士班 87 Randomization on testing in sequential logic circuits is more complicated and difficult than that on combinational logic circuits. In this thesis, it aims to adopt the method of Markov chain to analyze the random testability for detecting a fault in circuit. By the analysis results, the random testability of a circuit under test may be seen are a figure of merit and it can be used for generating a set of random test patterns to reduce the time of pattern generation. Jwu-E Chen 陳竹一 1999 學位論文 ; thesis 51 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 中華大學 === 電機工程學系碩士班 === 87 === Randomization on testing in sequential logic circuits is more complicated and difficult than that on combinational logic circuits. In this thesis, it aims to adopt the method of Markov chain to analyze the random testability for detecting a fault in circuit. By the analysis results, the random testability of a circuit under test may be seen are a figure of merit and it can be used for generating a set of random test patterns to reduce the time of pattern generation.
author2	Jwu-E Chen
author_facet	Jwu-E Chen Ti-Wen Chen 陳文
author	Ti-Wen Chen 陳文
spellingShingle	Ti-Wen Chen 陳文 Randomization on Testing in Digital Sequential Logic Circuits
author_sort	Ti-Wen Chen
title	Randomization on Testing in Digital Sequential Logic Circuits
title_short	Randomization on Testing in Digital Sequential Logic Circuits
title_full	Randomization on Testing in Digital Sequential Logic Circuits
title_fullStr	Randomization on Testing in Digital Sequential Logic Circuits
title_full_unstemmed	Randomization on Testing in Digital Sequential Logic Circuits
title_sort	randomization on testing in digital sequential logic circuits
publishDate	1999
url	http://ndltd.ncl.edu.tw/handle/54400850713916137407
work_keys_str_mv	AT tiwenchen randomizationontestingindigitalsequentiallogiccircuits AT chénwén randomizationontestingindigitalsequentiallogiccircuits AT tiwenchen shùwèixúnxùluójídiànlùcèshìdesuíjīxìng AT chénwén shùwèixúnxùluójídiànlùcèshìdesuíjīxìng
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Randomization on Testing in Digital Sequential Logic Circuits

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