Circuit Design of Built-In Self Testable and Repairable CMOS Memory Chips
碩士 === 國立成功大學 === 電機工程學系 === 87 === This thesis presents two novel circuit designs for memory testing. The first one is an exhaustive random test pattern generator (RTPG) that can provide exhaustive test patterns to different circuits through only one signal line. Therefore, this design c...
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| Format: | Others |
| Language: | en_US |
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1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/84290709088590445333 |
| Summary: | 碩士 === 國立成功大學 === 電機工程學系 === 87 === This thesis presents two novel circuit designs for memory testing. The first one is an exhaustive random test pattern generator (RTPG) that can provide exhaustive test patterns to different circuits through only one signal line. Therefore, this design can be used as an address generator for memory testing and can greatly reduce the routing area between the memory modules and the address generator. The second one is a build-in self-repair (BISR) scheme for the memory. It can automatically replace defective rows with spare rows without external assistance during testing. We have implemented this scheme using field programmable gate array (FPGA) to show the correctness and effectiveness of the design.
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