Circuit Design of Built-In Self Testable and Repairable CMOS Memory Chips

碩士 === 國立成功大學 === 電機工程學系 === 87 === This thesis presents two novel circuit designs for memory testing. The first one is an exhaustive random test pattern generator (RTPG) that can provide exhaustive test patterns to different circuits through only one signal line. Therefore, this design c...

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Bibliographic Details
Main Authors:	Ing-Heng Shih, 石穎衡
Other Authors:	Kuen-Jong Lee
Format:	Others
Language:	en_US
Published:	1999
Online Access:	http://ndltd.ncl.edu.tw/handle/84290709088590445333

id	ndltd-TW-087NCKU0442092
record_format	oai_dc
spelling	ndltd-TW-087NCKU04420922016-07-11T04:13:32Z http://ndltd.ncl.edu.tw/handle/84290709088590445333 Circuit Design of Built-In Self Testable and Repairable CMOS Memory Chips 內建式可自我測試及修復之CMOS記憶體晶片之電路設計 Ing-Heng Shih 石穎衡碩士國立成功大學電機工程學系 87 This thesis presents two novel circuit designs for memory testing. The first one is an exhaustive random test pattern generator (RTPG) that can provide exhaustive test patterns to different circuits through only one signal line. Therefore, this design can be used as an address generator for memory testing and can greatly reduce the routing area between the memory modules and the address generator. The second one is a build-in self-repair (BISR) scheme for the memory. It can automatically replace defective rows with spare rows without external assistance during testing. We have implemented this scheme using field programmable gate array (FPGA) to show the correctness and effectiveness of the design. Kuen-Jong Lee 李昆忠 1999 學位論文 ; thesis 73 en_US
collection	NDLTD
language	en_US
format	Others
sources	NDLTD
description	碩士 === 國立成功大學 === 電機工程學系 === 87 === This thesis presents two novel circuit designs for memory testing. The first one is an exhaustive random test pattern generator (RTPG) that can provide exhaustive test patterns to different circuits through only one signal line. Therefore, this design can be used as an address generator for memory testing and can greatly reduce the routing area between the memory modules and the address generator. The second one is a build-in self-repair (BISR) scheme for the memory. It can automatically replace defective rows with spare rows without external assistance during testing. We have implemented this scheme using field programmable gate array (FPGA) to show the correctness and effectiveness of the design.
author2	Kuen-Jong Lee
author_facet	Kuen-Jong Lee Ing-Heng Shih 石穎衡
author	Ing-Heng Shih 石穎衡
spellingShingle	Ing-Heng Shih 石穎衡 Circuit Design of Built-In Self Testable and Repairable CMOS Memory Chips
author_sort	Ing-Heng Shih
title	Circuit Design of Built-In Self Testable and Repairable CMOS Memory Chips
title_short	Circuit Design of Built-In Self Testable and Repairable CMOS Memory Chips
title_full	Circuit Design of Built-In Self Testable and Repairable CMOS Memory Chips
title_fullStr	Circuit Design of Built-In Self Testable and Repairable CMOS Memory Chips
title_full_unstemmed	Circuit Design of Built-In Self Testable and Repairable CMOS Memory Chips
title_sort	circuit design of built-in self testable and repairable cmos memory chips
publishDate	1999
url	http://ndltd.ncl.edu.tw/handle/84290709088590445333
work_keys_str_mv	AT inghengshih circuitdesignofbuiltinselftestableandrepairablecmosmemorychips AT shíyǐnghéng circuitdesignofbuiltinselftestableandrepairablecmosmemorychips AT inghengshih nèijiànshìkězìwǒcèshìjíxiūfùzhīcmosjìyìtǐjīngpiànzhīdiànlùshèjì AT shíyǐnghéng nèijiànshìkězìwǒcèshìjíxiūfùzhīcmosjìyìtǐjīngpiànzhīdiànlùshèjì
_version_	1718342137448235008

Circuit Design of Built-In Self Testable and Repairable CMOS Memory Chips

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