Application of the TOC’s Aggregated Buffer to the Due Date Control in the Semiconductor Wafer Fabrication

• Main Authors: Shang-Nan Huang, 黃商男
• Other Authors: Rong-Kwei Li
• Format: Others
• Language: zh-TW
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/94250628717060799128

碩士 === 國立交通大學 === 工業工程與管理系 === 87 === Due-date performance is one of the most important production performance indexes in wafer fabrication industry. This study try to develop a new method of shop flow scheduling for improves missed due-date performance. The traditional methods were addressed on cycle time estimation. Most of those papers use the estimated cycle time to forecast the completion time of the product, and then utilized the part’s slack time to schedule the lot’s priority. Unfortunately, few of those methods used in shop flow successfully. The concept of TOC aggregated time buffer was developed by A. Y. Goldratt in project management. This concept use the aggregated time buffer to protect the whole project’s due date instead of that only consider individual tasks. Therefore, this study aims to develop a new shop floor scheduling method base on the concept of TOC aggregated time buffer. This method is expected to reduce the mean tardiness and tardiness job’s. A simulation model with real world data is also established to examining the performance of the proposed method. The simulation result shows a better performance was obtained for rate of due date commitment, average tardiness, variance of average tardiness and average lateness when the shop floor control rule of the TOC’s aggregated time buffer is applied for different dispatching rules.