On Functional Coverage Analysis for Circuit Description in HDL
碩士 === 國立交通大學 === 電子工程系 === 87 === While simulating the HDL (hardware description language) designs, the verification coverage measurement can provide a quantitative analysis of the simulation completeness. By monitoring the execution of the HDL code during simulation, the verification en...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/75371277222295812516 |