Design of Phase Locked Loop with Spectrum Spread in Time Domain
碩士 === 國立交通大學 === 電子工程系 === 87 === This thesis describes the design of a Phase Locked Loop which is used in CPU to be the interface between external clock and internal clock, with the function of locking the external and internal clock phase to reduce the time delay between them, and also can be a f...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/20790873885438111160 |