Design of Phase Locked Loop with Spectrum Spread in Time Domain

• Main Authors: Hsiao-chyi Lin, 林小琪
• Other Authors: Jiin-chuan Wu
• Format: Others
• Language: zh-TW
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/20790873885438111160

碩士 === 國立交通大學 === 電子工程系 === 87 === This thesis describes the design of a Phase Locked Loop which is used in CPU to be the interface between external clock and internal clock, with the function of locking the external and internal clock phase to reduce the time delay between them, and also can be a frequency synthesizer to make internal clock multiple times of external clock. For reducing the influence of EMI to meet the regulative specification, we make use of some digital circuits to spread a few percents of PLL frequency spectrum in time domain, thus the peak value of power spectrum density will be lower down to an acceptable level without changing the total energy. This chip is designed using TSMC 0.6 mm SPTM CMOS process. Total die area excluding pad is 1000 5 1000 mm2. There are two PLL inside, the former one is used for spread spectrum, the later one is used for frequency synthesizer. It works under 3.3V power supply and input frequency is 14.318MHz. According to the simulation result, the operating frequency of VCO with 16 stages inside the former PLL is 28.636MHz; and that with 4 stages inside the later PLL is 2~256MHz.