Design of Phase Locked Loop with Spectrum Spread in Time Domain

Design of Phase Locked Loop with Spectrum Spread in Time Domain

碩士 === 國立交通大學 === 電子工程系 === 87 === This thesis describes the design of a Phase Locked Loop which is used in CPU to be the interface between external clock and internal clock, with the function of locking the external and internal clock phase to reduce the time delay between them, and also can be a f...

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Bibliographic Details
Main Authors:	Hsiao-chyi Lin, 林小琪
Other Authors:	Jiin-chuan Wu
Format:	Others
Language:	zh-TW
Published:	1999
Online Access:	http://ndltd.ncl.edu.tw/handle/20790873885438111160

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