A 1.25 Gbps CMOS Digital Transmitter
碩士 === 國立交通大學 === 電子工程系 === 87 === This thesis described the design of a 3.3 V CMOS digital transmitter that transmits 1.25 gigabit per second, which is composed of a 10 phase phase-lock-loop(PLL) clock generator, a 10 to 1 multiplexer and an output driver which drives 50 ohm. The digital...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/25618983778210901430 |