An ASIC Design of the Pipelined DFE for 100BASE-TX Ethernet Transceivers
碩士 === 國立交通大學 === 電信工程系 === 87 === The DSP-based design has gradually replaced the conventional analog approach in the 100BASE-TX transceiver. The main challenge for the the digital implementation is the requirement of high speed processing rate. In this thesis, the architecture and algor...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/59533722917326569865 |