Effects of Neutron Intrinsic Gettering (NIG) on Electrical

• Main Authors: Ching-Sang Chuang, 莊景桑
• Other Authors: Kuei-Shu Chang-Liao
• Format: Others
• Language: zh-TW
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/46834516335006966587

碩士 === 國立清華大學 === 工程與系統科學系 === 87 === There are basically three parts included in this research: 1. The effects of neutron intrinsic gettering in MOS Devices; 2. Electrical property improvement by NIG in MOS devices with Si3N4 passivation. 3. The effect of arsenic penetration on the electrical property in MOS devices. In the first part of this research, Si wafers are irradiated by fast neutron with different flux. A post annealing at 1100oC for 2~6 hr treatments were then performed. In this treatment, neutron intrinsic gettering (NIG) was obtained. We use these NIG-treated wafers as substrates and fabricate the MOS capacitors. As a result, both irradiation and annealing conditions have significant influence on the performance of the devices. There seems to be a trade off between them. Finally, the I44 (40hr-irradiation, 4hr annealing) sample possesses the best performance not only in the initial electrical property but also the endurance against hot carrier stressing and Co-60 radiation. For the second part, we intend to deposit Si3N4 films on the wafers before undergoing the neutron irradiation. These films will play the roles to prevent our Si substrates from the contaminants. Eventually, MOS capacitors will be fabricated. Electrical property measurements will be done to reconfirm the effects of NIG in MOS devices, and comparisons of the results between samples with or without Si3N4 passivation will also be illustrated. Moreover, the NAA (Neutron Activation Analysis) method will be used to qualitatively analyze the contamination sources. As a result, it shows that NIG is a technology with good reproducibility especially for the sample under 40hr-irradiation, 4hr annealing treatment. In the third part of this research, we will discuss the penetration effects of arsenic dopants which are the most commonly used impurities for the poly-Si gate doping of the NMOS devices in the recent industry. Besides, activation steps by rapid thermal annealing (RTA) after drive-in will also be discussed. As a result, samples with 50A gate oxide is affected by the penetration of arsenic under various drive-in conditions. From the results, 900oC for 20~30 min seems to be a good choice for the device fabrication. However, for the 35A-samples, the arsenic penetration effect does not seem to induce a damage to gate oxide quality. As for the part of activation by RTA, samples with RTA treatment have better performance, which means that better activation for the dopants is very important in the fabrication process.