Design of an FPGA for Field Programmable Multi-Chip System

• Main Authors: Su, Shih I, 蘇士益
• Other Authors: Feipei Lai
• Format: Others
• Language: en_US
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/12175045925209337574

碩士 === 國立臺灣大學 === 資訊工程學研究所 === 87 === In existing architecture, both the logic configuration and the network connectivity remain fixed for the duration of the emulation. Each emulated gate is mapped to one FPGA equivalent gate and each emulated signal is allocated to one FPGA pin. Thus for a partition to be feasible, the partition gate and pin requirements must be no greater than the available FPGA resources. This constraint yields the following possible scenarios for each FPGA partition: 1. Gate limited: no unused gates, but some unused pins. 2. Pin limited: no unused pins, but some unused gates. 3. No limited: unused FPGA pins and gates. 4. Balanced: no unused pins or gates. For mapping typical circuits onto available FPGA devices, partitions are predominately pin limited; all available gates can not be utilized due to the lack of pin resources to support them. Low utilization of gate resources increases both the number of FPGAs needed for emulation and the time required to emulate a particular design. Pin limits set a hard upper boundary on the maximum usable gate count any FPGA gate size can provide. This discrepancy will only get worse as technology scales; trends (and geometry) indicates that available gate counts are increasing faster than the available pin counts. Virtual wires not only increase usable bandwidth, but also relax the absolute limits imposed on gate utilization. The resulting improvement in bandwidth reduces the need for global interconnect, allowing effective use of low dimension interchip connection. And we will also introduce the new architectures of the switch block and logic block. It can both reduce the area of the FPGA and speed up the FPGA. We will discuss these features on the next chapters