The Design and Implementation of a 10-bit Pipelined Analog-to-Digital Converter
碩士 === 國立臺灣大學 === 電機工程學研究所 === 87 === In this thesis, a 10 bit, 20Msample/s pipelined analog-to-digital converter for video-rate applications is designed. The 1.5b/stage architecture with digital correction is adopted in this pipelined ADC. It consists of 9 stages in which only 19 compa...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/43559116988636945844 |