Chip Design and Implementation for High Speed ATM Adaptaion Layer Type 1 (AAL-1)
碩士 === 國立臺灣大學 === 電機工程學研究所 === 87 === This thesis describes a design of the ATM Adaptation Layer type 1(AAL1) chip for ATM network. The AAL1 segmentation and reassembly(SAR) chip are designed and implemented by the 0.6um SPTM CMOS process. The cell header of SAR-PDU is generated and proce...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/63569677159797841528 |