The Design and Implementation of a Viterbi Decoder Chip for CDMA Applications
碩士 === 國立臺灣科技大學 === 電子工程系 === 87 === In the thesis, the design and implementation of state-sequential VLSI architecture for Viterbi decoders is studied. Also, a new state partitioning approach based on a de Bruijn graph has been proposed for updating path metrics. Based on this approach,...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/47920635680904792593 |