| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 87 === In the thesis, the design and implementation of state-sequential VLSI architecture for Viterbi decoders is studied. Also, a new state partitioning approach based on a de Bruijn graph has been proposed for updating path metrics. Based on this approach, an efficient and programmable add-compare-select (ACS) architecture is designed. Furthermore, two survivor memory management schemes: shift register exchange and block trace back respectively, modified from the conventional methods, are proposed. The former can reduce the number of multiplexers and the area of routing wires; the latter can speed up decoding rate. Using these techniques, we had designed an R=1/2, K=9, g0 =753 , g1 =561 Viterbi decoder for CDMA personal communication services applications. The chip's core, consisting of approximately 152 K transistors, occupies 3.3 mm by 3.3 mm in a 0.6-um triple-layer-metal COMS technology. The chip's simulated data rate is 781.25 kbps with 25MHz clocking. The power dissipation is 890mW at a supply voltage of 5V.
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