Model Analysis and Circuit Implementation of Clock Generator Based on Charge-Pump Phase-Locked Loop
碩士 === 國立臺灣科技大學 === 電子工程系 === 87 === In this paper, we make some modifications in the original model of the charge-pump phase locked loop (PLL) and apply this modified model into the clock generator circuit. We also present the result of the practical circuit designed in this manner to v...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/30839649082902389189 |