Model Analysis and Circuit Implementation of Clock Generator Based on Charge-Pump Phase-Locked Loop

• Main Authors: Hung-Jen Chien, 簡宏仁
• Other Authors: Hwan-Mei Chen
• Format: Others
• Language: zh-TW
• Published: 1999
• Online Access: http://ndltd.ncl.edu.tw/handle/30839649082902389189

碩士 === 國立臺灣科技大學 === 電子工程系 === 87 === In this paper, we make some modifications in the original model of the charge-pump phase locked loop (PLL) and apply this modified model into the clock generator circuit. We also present the result of the practical circuit designed in this manner to verify this modified model. The parameters of this PLL circuit include : the charge pump current (Ip), resistor (R) & capacitor (C) values of the loop filter, the gain (Kv) of the current-controlled oscillator (CCO) and the N-number of the divider. All of the parameters mentioned previously can be implemented by the derived stability and overload figure of our PLL system. This PLL chip is fabricated by 0.6um SPTM process, and it can generate 64MHz clock signal with 25us of locked time. The oscillating frequency range of the CCO is from 120MHz to 320MHz. In this chip, the maximum power dissipation is about 40mW, and the area is about 520um650um.