Design of 1.5V 10-bit 10MHz Pipelined Analog-to-Digital Converter
碩士 === 淡江大學 === 電機工程學系 === 87 === In this thesis, a 1.5V low voltage pipelined analog-to-digital converter(ADC) is proposed and designed. Because the channel length of MOS is shorten in deep sub-micron process, the supply voltage should be reduced, The trend of the supply voltage of digital circuit...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
1999
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| Online Access: | http://ndltd.ncl.edu.tw/handle/05918920981338251685 |