| Summary: | 碩士 === 淡江大學 === 電機工程學系 === 87 === In this thesis, a 1.5V low voltage pipelined analog-to-digital converter(ADC) is proposed and designed. Because the channel length of MOS is shorten in deep sub-micron process, the supply voltage should be reduced, The trend of the supply voltage of digital circuit is toward lower voltage, 1.5V or even lower. In mixed-mode VLSI design, the supply voltage of digital parts and analog parts had better to be the same. Therefore the low voltage analog-to-digital converter (ADC) needs to be studied
The pipelined ADC is mainly constructed by switching capacitors (SC) gain stages, The traditional analog switch can not work under lower operation voltage (1.5V), therefore we utilize a boot strape circuit in clock pulse generator to overcome this problem. In the design of low voltage operational amplifier (OPAMP), the voltage swing of input and output is critical for the performance. A common source gain stage is added in the output stage to get a better output swing and enhance the DC gain as well. Because the close loop of the OPAMP circuit is formed by negative amplification configuration, the input common mode voltage range is not important in the low-voltage operation. The OPAMP is not needed in the sampling period of sample-and-hold circuit. Therefore, we add a switch in the output stage of the OPAMP to control the static to reduce power dissipation current. By this arrangement, the static power dissipation could reduced about 40%.
The HSPICE simulation shows that the resolution of this ADC is 10-bit, the sampling rate is 10MHz, and the power consumption is 15mW in 1.5V supply voltage. This ADC is designed and will implemented by TSMC 0.35um mixed-signal process.
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