壓電阻應力計之特性分析與電子構裝熱應力量測

• Main Author: 林玉翎
• Other Authors: 羅本吉吉
• Format: Others
• Language: zh-TW
• Published: 2000
• Online Access: http://ndltd.ncl.edu.tw/handle/03280059365770395991

碩士 === 中正理工學院 === 電子工程研究所 === 88 === As die size continuously increases in modern IC and the circuit density goes higher, problems due to packaging induced stress become important for modern microelectronic industry. Therefore, engineers need to construct a stress-monitoring tool to evaluate the magnitude of the stress induced during various packaging processes. Reports on piezoresistive sensors for evaluating package-induced stress are available in the literatures, but studies on the piezoresistive’s characteristics are insufficient. This thesis tries to take a step to fill the gap. There are three studies emphasized in this paper: First, piezoresistors with three different resistance were designed in order to find out which resistance value is more suitable to be used as stress-monitoring tool. Secondly, silicon strips were cut from wafer at a specific angle to extract the entire piezoresistive coefficients. Thirdly, test chips with piezoresistive sensors were packaged into various types of PQFP, then relationships between environment temperature and chip power vs. stress were measured to analyze stress induced due to packaging processes. After analyzing piezoresistive coefficient with resistance between 15kΩ and 55kΩ, it was found that the variations of the piezoresistive coefficients are small. Thus, the piezoresistor with smaller resistance is recommended so that the space of the chip layout can be increased. For the second part of this research, it was found that though p-type piezoresistor is more sensitive to stresses, the standard deviation of the piezoresistor coefficient is too large. On the other hand, N-type piezoresistor is more suitable as stress-monitoring tools to evaluate stress induced during packaging processes due to its smaller standard derivation. After measuring package-induced stresses on several batches of testing samples, it is found that stress diversity is large at different chip positions as well as difference batches of the package.