Power Minimization in LUT-Based FPGA Technology Mapping
碩士 === 中原大學 === 資訊工程學系 === 88 === The field programmable gate array (FPGA) is a relatively new technology in VLSI designs. One of the important steps in the design flow of FPGAs is technology mapping. For lookup table (LUT) based FPGAs, technology mapping is the process of transforming the given cir...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/23470252803819917469 |