Lot Release and Dispatching Model in Photolithography Area under the Limitation of Stepper Grouping
碩士 === 國立交通大學 === 工業工程與管理系 === 88 === In semiconductor manufacturing, increasing device density by shrinking feature size towards deep sub-microns is the tendency for IC (Integrated Circuit) function enhancement and cost reduction. In this technology trend, photolithography becomes the most critical...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/98850258131484169428 |