| Summary: | 碩士 === 國立交通大學 === 工業工程與管理系 === 88 === In semiconductor manufacturing, increasing device density by shrinking feature size towards deep sub-microns is the tendency for IC (Integrated Circuit) function enhancement and cost reduction. In this technology trend, photolithography becomes the most critical area in wafer process. In order to reduce the impact of tight process requirement, such as overlay in lithography, Stepper Grouping System is normally implemented to avoid machine-to-machine variation. Stepper Grouping System requires all critical layers to use the same stepper. It means if the first critical layer of lithography process uses stepper #1, the other critical layers will have to use this stepper later on to reduce process variance. This limitation can guarantee process stability. But it makes production control very complicate because of less flexibility.
Due to the stepper grouping limitation and the fact that steppers are normally the bottleneck in wafer fabrication, this research will focus on the development of wafer release and dispatching model to reduce production impact that comes from stepper grouping. To balance loading and keep WIP for each stepper are the key points of wafer release and dispatching model that developed in this research respectively.
Simulation results shows the model developed in this study gives better performance than the others tested rule in terms of stepper utilization, throughput, and cycle time.
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