Design and Analysis of CMOS Two-Step High Speed A/D Converter
碩士 === 國立交通大學 === 電子工程系 === 88 === This thesis proposes a 5Volt, 8bits, 25MS/sec CMOS A/D converter which is implemented by the two—step architecture. This structure consists of coarse comparators, fine comparators, digital error correction circuit, switch array circuit and clock generator....
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2000
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| Online Access: | http://ndltd.ncl.edu.tw/handle/87728420595980085808 |